Introduction
- Overview of workshop and SHARC processor
Software Development
- Getting started with VisualDSP++; creating and configuring projects; configuring build and debug tools.
- Writing and debugging C programs.
- Software simulation; simulate a system using input and output data streams; simulate interrupts.
SHARC Architecture
- How to efficiently utilize the SHARC's core architecture when writing code. The SHARCs simple to understand algebraic syntax assembly code is used to demonstrate the core's functionality. Covered are, data formats, arithmetic operations, internal memory, data addressing, program sequencing.
Advanced Instructions and Optimizations
- Parallel and Multi-function assembly instructions, architectural and programming optimization techniques.
DMA
- How to efficiently move data using the DMA engine.
- Features of the DMA engine.
- How to set and initiate DMA transfers.
External Parallel Interface
- Interfacing to external devices, SDRAM, SRAM, Memory Mapped peripherals and data throughputs.
On Chip Peripherals
- How to set and use all the on-chip peripherals
Booting Process
- Learn the different booting methods supported by the SHARC.
- Learn how to generate a bootable file
Advanced Linker Functions
- Show how set up the software for a system with shared memory, and a system which uses code and/or data overlays
System Considerations
- Covers hardware issues such as reset, power, unused pins
Introduction to VisualDSP++ Basics.
Demonstrating the fundamentals of the VisualDSP++ development environment. Basic skills using the compiler, assembler and debugger for a particular EZ-Kit Lite. Requires ability to handle simple "C/C++" and assembler programs.
DSP algorithm development within a "C/C++" (high level) environment.
Developing and testing a basic DSP algorithm written in "C/C++". This permits us to investigate the best approaches to handling memory access, loops, circular buffer without specialized hardware support. Examination of the assembly code produced by the compiler for various compiler and assembler options. Will provide results that can be used to test assembly code functions developed in second laboratory.
DSP algorithm development within an assembly language (low level) environment.
The concepts developed in Laboratory 1 are changed to take advantage of the architecture of the processor. Introduction to high level (C/C++) -- low level (assembly) interface and hardware circular buffers, etc.
Optimized DSP algorithm development.
In this laboratory we look at techniques to take advantage of the full parallel capability of the DSP processor. Examination of the advantages and limitations of various processor architecture.
Optimized processor use.
Putting the skills together. Student developed project to demonstrate an understanding of how to take advantage of all the functionality of the processor -- background DMA activity and double/triple buffering etc.
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