FPGA/CPLD System Design Using Xilinx & Altera
Two day work shop on
FPGA/CPLD System Design Using Xilinx & Altera
Day1
Session |
Time |
Topic |
Speaker |
I |
09.30 – 11.00 am |
Introduction to ASIC & FPGA |
|
II |
11.00 - 11.15 am |
Break |
|
|
III |
11.15 – 11.45 am |
Design Flow OF Xilinx ISE |
|
|
IV |
11.45 – 12.30 a.m |
Introduction to Xilinx Allied tools |
|
|
12.30 – 01.30 p.m |
Lunch Break |
|
|
V |
1.30 to 3.00 |
Demos on Xilinx ISE
(up to Simulation level) |
|
|
3.00 to 3.15 |
Break |
|
|
VI |
03.15 – 04.30 p.m |
Demos on Xilinx ISE
(Implementation) |
|
Day 2
Session |
Time |
Topic |
Speaker |
I |
09.30 – 10.15 am |
Introduction to EDK |
|
II |
10.15 – 11.00 am |
Design Flow Of EDK |
|
|
11.00 - 11.15 am |
Break |
|
III |
11.15 – 11.45 am |
Demos on Xilinx platform studio |
|
IV |
11.45 – 12.30 a.m |
Introduction to Quartus II |
|
|
12.30 – 01.30 p.m |
Lunch Break |
|
V |
1.30 to 3.00 pm |
Introduction to NIOS |
|
|
3.00 to 3.15 |
Break |
|
|
VI |
3.15 to 4.30 |
Demos on Quartus II tool & Debugging |
|
Who can attend?
B.E Final year ECE, EEE & M.E
Prerequisite
Should have fundamental knowledge on Microprocessor and Computer Architecture.
|
