HDVLSI

Module I ( Intorduction to Digital System )

• Digital System Overview
• Design Of Combinational Logic Circuits and Sequential Logic Circuits
• Study Of FSM and Synchronous & Asynchronous design
• Various Coding Methods
• Types Of device to Implement the Logic

Module II ( Fundementals Of FPGA & CPLD Design )

• Overview Of Altera's FPGA & CPLD Families
• Overview of Xilinx FPGA & CPLD Families
• Identify the I/O Resources available in CPLD & FPGA

Module III ( Logic Design Using to VHDL)

• Hardware Overview Modelling
• Concurrent & Sequential Statements
• Package Declaration & Test Bench Design
• Practise RTL VHDL code for synthesis
• Target & Optimize FPGA / CPLD by Using VHDL

Module IV ( Logic Design Using to Verilog)

• Verilog Language Concept
• Verilog Tasks & Functions
• Develop the Test Benches and Stimulate their Design
• Implement & Download the Target devices

Module V ( Development Tools)

• Xilinx ISE Design Tool
  • Examine the Xilinx Project Navigator GUI
  • Determine the Synthesis Report
  • Use the PACE tomake the PIN Assignment
• Atera Quartus II Tool
  • Create & Compile Quartus IIProjects
  • Assign Clock & I/O constraints to improve the Design Performance
  • Review the Compilation & Simulation Results

Module VI ( Embedded Systems Development )

• Xilinx Platform Studio (XPS)
  • EDk Overview And Base System Builder
  • Hardware Design Using EDK
  • Create and Integrate Your Own IP intoEDK Environment
• NIOS II IDE
  • Create Software Projects for the NIOS II processor using the NIOS II IDE
  • Configure the NIOS II IDE Embedded Procesor Using Quatrus II Software

Lab Description

Exercise 1

• Static timing analysis of  Ascending order & Descending order program using Xilinx ise 8.2i tool and timing performance chart is prepared.

Exercise 2

• File I/O concept  is used in image filtering module and the output is verified

Exercise 3

• Briefing the usage, purpose and advantage of various packages and conversion functions using various programs.

Exercise 4

• Three important design entry methods(HDL language,schmetics,statecad) are tried with same project and each of its advantages have been analysed.

Exercise 5

• All the possible test bench conditions are tested for various experiments.

Exercise 6

• Driver codes for display peripherals like LCD, GRAPHICAL LCD and seven segments are written and checked for the display. Also various image and character display can be tried.

Exercise 7

• Extensive IP core collection is utilized with various modules and various FPGA chip. The complete analysis chart is made.

Exercise 8

• Different types of memory interfaces like sram, will be tried out and various ranges of data from images to code is stored in it and retrieved back.

Exercise 9

• Real time analog data’s are converted and used in our experiments. It has been tried out for various types of convertor Ic and FPGA chips.

Exercise 10

• The full clock range from 25mhz to 200 mhz is used in the project by developing  clock design manager(DCM)

Exercise 11

• The internal architectural  blocks like Block ram and distributed ram of the FPGA chip is extensively used in the projects by developing appropriate code and its various advantageous are examined.

Exercise 12

• simple module is developed and bit stream is download into the FPGA chip using various.

Exercise 13

• Different types of communication protocol is developed and verified for different applications.

Exercise 14

• The multiplier and multiplexer unit inside the FPGA chip is used and verified for  different purpose.

Exercise 15

• Customize BSB module development using EDK Tool

Exercise 16

• Different image processing algorithm is implemented using EDK Tool.

Exercise 17

• Various wave form generation and speed control of various types of motor using  Altera cyclone processor.

Exercise 18

• Working with Wireless modules and implementation of simple mathematical algorithms using cyclone processor.

Exercise 19

• Audio decoding and Encoding using Quartus ll

Exercise 20

• controlling of VGA using cyclone processor under Nios processor environment.

MINI PROJECT

Analysis of project requirements – Collection of necessary data – Possible conversion to HDL language constraints – HDL coding – Debugging the code – Verification using simulation – Applying various test conditions – Generating simulation report

MAIN PROJECT

Analysis of project requirements – Collection of necessary data – Possible conversion to HDL language constraints – HDL coding – Debugging the code – Verification using simulation – Applying various test conditions – synthesizing the code to the available FPGA chip – analysizing the synthesis report generated – listing the resource utilized  and constraints taken into account -  recoding for least utilization of resource using FPGA editor or FPGA floor planner(if necessary) – Applying necessary constraints required for the project – translate – map – route – configuring the bit file into the FPGA chip – verifying the real time output