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VLSI Projects - IEEE 2013

IEEE 2013

TESTING | DFT

CMOS | MEMORY DESIGN

Sl.No.

PROJECT THEME

APPLICATION

1

Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays

Avionics

2

LFSR-Reseeding Scheme For Achieving Test Coverage

Cellular Telephony

3

DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM cell for High Speed CMOS Circuits

Microchip Manufacturing

4

Used self-controllable Voltage Level technique to reduce leakage current in DRAM 4x4 in VLSI

Microchip Manufacturing

IEEE 2013

CADENCE

LOW POWER DESIGN | CMOS | SEQUENTIAL, ARITHMETIC, DIGITAL AND ANALOG CIRCUITS

5

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic

Photovoltaics

6

Logical Effort for CMOS-Based Dual Mode Logic Gates

Microchip Manufacturing

7

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

Photovoltaics

8

Low-power high-speed full adder for portable electronic applications

MEMS

9

Low-Power Digital Signal Processing Using Approximate Adders

Power Management

10

Activity-Driven Fine-grained Clock Gating and Run Time Power Gating Integration

Microchip Manufacturing

11

A Novel Flip-Flop Design for Low Power Clocking System

Avionics

12

Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology

Microchip Manufacturing

3

Leakage Minimization of 10T Full Adder Using Deep Sub-Micron Technique

Microchip Manufacturing

14

Asynchronous Design of Energy Efficient Full Adder

Photovoltaics

15

Design of a Low-Power Pulse-Triggered Flip-Flop with Conditional Clock Technique

RF & MEMS

16

Design of High Speed and Low Power 15-4 Compressor

Avionics

17

Analysis and design of a Low-Voltage Low-Power Double-tail Comparator

Avionics

18

Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology

Avionics

19

Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop

Photovoltaics

20

Comparative Analysis For Hardware Circuit Architecture Of Wallace Tree Multiplier

Microchip Manufacturing

IEEE 2013

SPARTAN 3AN

REAL-TIME APPLICATONS (GPS,GSM,ZIGBEE,RF)

21

Rescue robo

Machine Vision

22

License Plate Recognition For Toll Gate System

Electronic Article Surveillance

23

Improved number plate localization algorithm and its efficient field programmable gate arrays implementation

Electronic Article Surveillance

24

Prototype of a Fingerprint Based Licensing System For Driving

Machine Vision

25

Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing

Machine Vision

26

Secure Transmission in Downlink Cellular Network with a Cooperative Jammer

Signal Jamming

27

A Smarter Toll Gate Based on Web Of Things

Electronic Article Surveillance

28

An Interactive RFID-based Bracelet for Airport Luggage Tracking System

Asset Tracking

29

RFID-based Location System for Forest Search and Rescue Missions

Machine Vision

30

Design and Implement of Real-time Monitoring System of Urban Water Supply

Remote Monitoring

IEEE 2013

SPARTAN 6

EDK | SOFT CORE PROCESSOR DESIGN

31

FPGA Based Embedded Webserver Using Microblaze Processor

Automotive Infotainment

32

Exploration of Multi-thread Processing on XILKERNEL for FPGA Based Embedded Systems

Automotive Infotainment

33

Energy Efficient Image Transmission

Machine Vision

34

Fast FPGA-Based Multi-object Feature Extraction

Computer Vision

35

“ i ” - A novel algorithm for Optical Character Recognition (OCR)

Vehicular Networking

36

Hardware Implementation of a Digital Watermarking System for Video Authentication

Defence

37

Reconfigurable Processor for Binary Image Processing

Machine Vision

38

FPGA Implementation of Pipelined Architecture For SPIHT Algorithm

Biomedical Signal

39

Least Significant Bit Matching Steganalysis Based on Feature Analysis

Defence

IEEE 2013

COMMUNICATION

PROTOCOL DESIGN

40

Implementation of I2C Master Bus Controller on FPGA

Networking Line Card

41

Pipelined Radix-2K Feed forward FFT Architectures

Radar

42

Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT

OFDM

43

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

Computer Networking

IEEE 2013

SPARTAN 6

BIOMEDICAL

44

Design of Sobel Operator Using Field Programmable Gate Arrays

Machine Vision

45

Modified Gradient Search for Level Set Based Image Segmentation

Bio-Medical

46

Selective Eigen background for Background Modeling and Subtraction in Crowded Scenes

Computer Vision

IEEE 2013

SPARTAN 6

BIOMEDICAL

47

FPGA Implementation of Moving Object Detection in Frames by Using Background Subtraction Algorithm

Computer Vision

48

Realization of Beamlet Transform Edge Detection Algorithm using FPGA

Computer Vision

49

An Analysis of SOBEL and GABOR Image Filters for Identifying Fish

Machine Vision

IEEE 2013

SPARTAN 6

NON LINEAR FILTERS

50

Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT

Computer Vision

51

Optical Flow Estimation for Flame Detection in Videos

Computer Vision

52

An Efficient Denoising Architecture for Removal of Impulse Noise in Images

Computer Vision

53

Design and Implementation of Hardware Architecture for Denoising Using FPGA

Computer Vision

IEEE 2013

NETWORK SECURITY

54

Performance Analysis of Encryption Algorithms for Information Security

Defence

55

Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware

NSA Products

56

Parallel AES Encryption Engines for Many-Core Processor Arrays

NSA Products

IEEE 2012

TESTING

LOW POWER DESIGN CIRCUITS | TANNER EDA S-EDIT & W-EDIT

57

FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL

Microchip Manufacturing

58

Optimization of Microcode Built-In Self Test By Enhanced Faults Coverage for Embedded Memory

Microchip Manufacturing

59

Low-Power and Area-Efficient Carry Select Adder

Power Management

60

Designing and Simulation of Full Adder Cell Using FINFET Technique

Avionics

61

A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique

Avionics

62

A Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI Design

Microchip Manufacturing

63

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Photovoltaics

64

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock
Distribution Networks

MEMS

65

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

Microchip Manufacturing

66

Single Phase Clocked Quasi Static Adiabatic Tree Adder

Photovoltaics

IEEE 2012

BIOMETRIC

WSN

67

An Embedded Real-Time Finger-Vein Recognition System for Mobile Devices

Machine Vision

68

Gesture Recognition Using Field Programmable Gate Arrays

Machine Vision

69

An improved three-factor authentication scheme using smart card with biometric privacy protection

Machine Vision

70

Platform-Independent Customizable UART Soft-Core

Modems

IEEE 2012

SIGNAL PROCESSING

CORE PROCESSOR DESIGN | CRYPTOGRAPHY

71

BPSK System on Spartan 3E FPGA

WLAN,Bluetooth

72

Design of an error detection and data recovery architecture for motion estimation testing applications

Computer Vision

73

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation

Radar

74

Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS

Automotive Infotainment

75

Analysis of CT and MRI Image Fusion using Wavelet Transform

Bio-Medical

76

A Level Set Based Deformable Model for Segmenting Tumors in Medical Images

Machine Vision

77

Edge Detection of Angiogram Images Using the Classical Image Processing Techniques

Machine Vision

78

FPGA Hardware of the LSB Steganography Method

Defence

79

An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion

Computer Vision

80

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Biomedical

81

A Level Set Based Deformable Model for Segmenting Tumors in Medical Images

Biomedical

82

A Novel Architecture for VLSI Implementation of RSA Cryptosystem

Defence

83

An efficient FPGA implementation of the Advanced Encryption Standard Algorithm

NSA Products

84

A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL

NSA Products