Introduction to Verilog

Course Description

     This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

     In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level

• Fundamental to Intermediate

Training Duration

• 40 hours

Who Should Attend?

• Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisites

• Basic digital design knowledge

Software Tools

• ALTERA Quartus II Software

Skills Gained

      After completing this training, you will be able to:     

• Write RTL Verilog code for synthesis
• Write Verilog test fixtures for simulation
• Create a Finite State Machine (FSM) by using Verilog
• Target and optimize Xilinx FPGAs by using Verilog
• Use enhanced Verilog file I/O capability
• Run a timing simulation by using Xilinx Simprim libraries
• Create and manage designs within the ISE software design environment
• Download to the Spartan®-3E FPGA 1600E demo board

Course Outline      

• Introduction to Digital Systems
• Difference between digital and analog design
•  Basic Gates, Combinational logic design, how to design combination logic
•  Sequential logic, Synchronous & Asynchronous
•  FSM, Sequential designs, Mealy & Moore machine
• Projects on FSM Language elements
• Gate level modeling
•  User defined primitives Blocking & Non-blocking assignments
•  Timing controls, File IO, Compiler directives  Data flow, Behavioral, Structural modeling
•  Tasks, Functions, Verification, Test bench design & stimulus, VERILOG Synthesis, Coding style

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that you will verify in simulation

• Static timing analysis of Ascending order & Descending order program using QUARTUS II tool and timing performance chart is prepared.
• File I/O concept is used in image filtering module and the output is verified.
• Briefing the usage, purpose and advantage of various packages and conversion functions using various programs.
• Three important design entry methods (HDL language, schematics, state cad) are tried with same project and each of its advantages have been analyzed.
• All the possible test bench conditions are tested for various experiments.

MINI PROJECT

• Analysis of project requirements
•  Collection of necessary data
•  Possible conversion to HDL language constraints
•  HDL coding
•  Debugging the code
•  Verification using simulation
• Applying various test conditions
• Generating simulation report.