Course Description

Learn the FPGA design flow for implementing DSP designs. You will use DSP Builder which is an interface between the Quartus® II software v. 8.1 & Mathworks` Matlab & Simulink tools. You will analyze, design, implement, & verify DSP systems using the DSP Builder blockset in Matlab & Simulink. You will increase simulation speed by co-simulating a design with a FPGA board using Hardware in the Loop feature. With a link for ModelSim® feature, you will co-simulate ModelSim RTL-level models from within Simulink. By exploiting Matlab & Simulink interoperability, you will parameterize & verify a DSP Algorithm from the system level. You will incorporate IP MegaCore® cores in your design.

At Course Completion

You will be able to:

• Implement DSP algorithms using Altera® DSP Builder
• Parameterize DSP Builder blocks using MATLAB
• Perform RTL simulation using ModelSim-Altera
• Increase simulation speed via hardware-in-the-loop
• Perform system-level simulation using MATLAB script
• Understand the Avalon Streaming Interface

Skills Required

• Background in digital logic design
• Familiarity with DSP fundamentals and design
• Familiarity with Altera® FPGA architecture is helpful, but not necessary
• Familiarity with Mathworks Matlab and Simulink are helpful, but not necessary

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• DSP Designer